There are many useful circuits that require an arithmetic operation (e.g., an addition operation) followed by a conversion to a thermometer code or the like. Such circuits can, for example, serve as the last stage before a digital to analog converter (DAC), or the loop filter in a digital phase locked loop (DPLL) or digital delay locked loop (DDLL). While binary arithmetic is efficient at computing numbers, thermometer codes are known to have advantageous properties when it comes to interfacing to analog systems.
The main advantage of the thermometer code is that it is monotone, i.e., between individual codes, there exists only a transition of one bit from one code state (e.g., zero) to the other code state (e.g., one). For example, given a three-bit binary code transition from 011 (decimal 3) to 100 (decimal 4) wherein one bit transitions from zero to one and other bits transition from one to zero, the corresponding thermometer code transition may be 00000111 to 00001111. Since only one bit transitions from a zero to a one in the thermometer code, less errors typically would occur in any output signal that the thermometer code may represent (e.g., a frequency or phase signal), thus yielding an advantage in the thermometer code as compared with the binary code.
FIG. 1 shows a phase correction portion of a conventional DPLL, typically used by a digital data receiver in a communication system. As is known, a DPLL circuit typically includes a serial shift register which receives digital input samples (extracted from a signal received from a digital data transmitter), a stable local clock signal which supplies clock pulses to the shift register to drive it, and a phase correction circuit which takes the local clock and regenerates a stable clock in phase with the received signal by adjusting the phase of the regenerated clock to match the received signal. The regenerated clock signal is then used to sample the received data and determine the value of each received bit. When a signal is first received, the regenerated clock and the received signal will not be aligned. The loop therefore starts to track the received signal, and eventually locks-in to the required signal, allowing it to find the center of each received data bit, and reliably decode the received information.
A loop filter is used by the phase correction circuit of the DPLL to compute the new frequency that is required by the input, on a cycle by cycle basis. An error signal is passed to the loop filter. The error signal may be representative of a frequency error and/or a phase error. Frequency error is a representation of whether the reference frequency is higher or lower than the output frequency of the DPLL, and optionally by what amount it is higher or lower. Phase error is a representation of whether the reference clock edge arrived earlier or later than the output clock edge, and optionally by what amount.
Arithmetic implementation of a digital loop filter is typically performed in binary, and the result is separated into most significant bits (MSB) and least significant bits (LSB). That is, as shown in FIG. 1, the digital filter has an MSB filter component 102 and an LSB filter component 104.
The MSB portion of the loop filter output is encoded as two groups of thermometer codes in binary-to-thermometer encoder 106, which are sent to digitally controlled oscillator (DCO) array 110. As is known, the two groups of thermometer codes are used for row and column control of the DCO. Note that encoder 106 outputs two sets of 2N/2 bits, where N is the number of bits in the MSB. This is a reduction from a straightforward thermometer code representation, that would require a set of 2N bits (for N=8, we reduce from 256 bits to 16+16=32 bits). This reduction is a standard technique that is commonly used. The LSB portion of the loop filter output is further encoded using sigma delta (SD) encoder 108, and sent to the DCO as a dithering signal.
However, there are several problems with the above-described DPLL implementation. First, arithmetic operations need to be done at the full resolution of the filter, however, the error signal is usually very small. Second, binary-to-thermometer encoders are relatively large in size, and require a significant amount of fan-out from the input signals. Further, the fan-out increases exponentially with the magnitude of the input, and therefore does not scale well for larger codes. Still further, the conversion to thermometer code can not start until the arithmetic computation is completed, thus potentially increasing the latency inside the DPLL control loop. This increased latency may have negative effects on the stability of the closed loop.
Accordingly, it would be desirable to provide improved techniques for processing a binary coded signal to generate a thermometer coded signal.